BiDIFS and CoDEBTS: Exploiting Compiler-Processor Interaction for Performance Enhancement

This paper presents a novel approach towards the architecture of a 32-bit RISC pipeline and a compiler for it, which aim to improve performance by ldquoreducing the stalls caused by branch hazardsrdquo. It presents two techniques - Bimodal Dual-Instruction Fetch Stage (BiDIFS) and Compiler Dependent Branch Target Stack (CoDeBTS). CoDeBTS is a prediction scheme which give close to 100% accurate prediction for the specific types of branches that they are suggested for, whereas BiDIFS is a novel architecture that has no branch penalties. Both the techniques aim to exploit the advantages of modern compilers coupled with architectures specifically targeted for being able to use the valuable information that is gathered by the compiler in its various phases especially semantic analysis. Compiler Processor interaction techniques have enormous potential for improving both performance and reducing power consumption, here we propose just two of them. Both the architectures are proposed, implemented and evaluated.