DocumentCode
2533022
Title
Improving analog circuit fault diagnosis by testing points selection
Author
Ossowski, Marek ; Korzybski, Marek
Author_Institution
Tech. Univ. of Lodz, Lodz, Poland
fYear
2012
fDate
18-21 Sept. 2012
Firstpage
1
Lastpage
4
Abstract
This paper describes two different methods of improving the ranking list algorithm for catastrophic faults localization method. First one, based on the simulated annealing and the genetic algorithm approach, enables us to search in very large set of possible testing points. Second one is established on the invented fitness function closely related to the structure of modified GRA algorithm. Both methods enable us to investigate circuits with parameter´s tolerances included. Presented simple filter-wrapper approach for finding the set of analyzed circuit features may be also used for improving any other fault function defined for the proposed ranking list method.
Keywords
analogue circuits; circuit testing; fault diagnosis; genetic algorithms; simulated annealing; analog circuit fault diagnosis; catastrophic faults localization method; fault function; filter-wrapper approach; genetic algorithm approach; invented fitness function; modified GRA algorithm; ranking list algorithm; simulated annealing; testing points selection; Algorithm design and analysis; Circuit faults; Classification algorithms; Fault diagnosis; Simulated annealing; Testing; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals and Electronic Systems (ICSES), 2012 International Conference on
Conference_Location
Wroclaw
Print_ISBN
978-1-4673-1710-8
Electronic_ISBN
978-1-4673-1709-2
Type
conf
DOI
10.1109/ICSES.2012.6382247
Filename
6382247
Link To Document