A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique

Author

Jen-Shiun, Chiang ; Pao-Chu, Chou

Author_Institution

Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan

fYear

1998

fDate

24-27 Nov 1998

Firstpage

1

Lastpage

4

Abstract

We propose a multistage fourth order sigma-delta (ΣΔ) modulator with reduced sensitivity to the gain of operating amplifier. In the low voltage high order ΣΔ modulator, the gain of the operating amplifier is usually the most critical problem of the design. In order to overcome the difficulties of the high gain low voltage operating amplifier, we try to use medium gain operating amplifiers to design a fourth order multistage ΣΔ modulator, and find that it functions very well. The modulator is realized in a 0.5 μm DPDM process with an active area of 1.8 mm². The HSPICE simulation shows this ΣΔ modulator with a maximum signal-to-noise-ratio (SNR) of 91 dB

Keywords

SPICE; circuit simulation; compensation; operational amplifiers; sigma-delta modulation; 0.5 micron; 3.3 V; DPDM process; HSPICE simulation; active area; gain compensation technique; maximum signal-to-noise-ratio; medium gain; operating amplifier; two-stage fourth-order sigma-delta modulator; Analog-digital conversion; Delta modulation; Delta-sigma modulation; Energy consumption; Low voltage; Multi-stage noise shaping; Operational amplifiers; Quantization; Signal resolution; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on

Conference_Location

Chiangmai

Print_ISBN

0-7803-5146-0

Type

conf

DOI

10.1109/APCCAS.1998.743643

Filename

743643