Title :
LV/LP CMOS high speed analog multiplier
Author :
Hyogo, Akira ; Hwang, Changku ; Ismail, Mohammed ; Sekine, Keitaro
Author_Institution :
Dept. of Electr. Eng., Sci. Univ. of Tokyo, Japan
Abstract :
In this paper we propose a new LV/LP four quadrant analog multiplier. The multiplier is composed of a LV/LP CMOS composite cell with two high input impedance terminals (LVLPCCC) which has a square-law current-voltage characteristic. SPICE simulation results using MOSIS 2 μm n-well process parameters show that the multiplier achieves a maximum differential input voltage of 2Vpp, f-3 dB of 250 MHz and power consumption of 1.17 mW with a 3 V supply. Also, simulated Total Harmonic Distortion (THD) less than 1% at frequency up to 8 MHz for 2 Vpp input voltage is obtained
Keywords :
CMOS analogue integrated circuits; analogue multipliers; harmonic distortion; high-speed integrated circuits; low-power electronics; 1.17 mW; 2 V; 2 micron; 250 MHz; 3 V; CMOS analog multiplier; CMOS composite cell; LV analog multiplier; MOSIS n-well process; SPICE simulation; THD; current-voltage characteristic; four quadrant analog multiplier; high input impedance terminals; high speed analog multiplier; low power multiplier; low voltage operation; square-law I-V characteristic; total harmonic distortion; Frequency response; MOSFET circuits; Threshold voltage; Transconductance;
Conference_Titel :
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location :
Chiangmai
Print_ISBN :
0-7803-5146-0
DOI :
10.1109/APCCAS.1998.743648
