Title :
An improved pass transistor synthesis method for low power, high speed CMOS circuits
Author :
Vinereanu, Tudor ; Lidholm, Sverre
Author_Institution :
Nat. Microelectron. Res. Centre, Univ. Coll. Cork, Ireland
Abstract :
A synthesis method for generating hybrid pass gate circuits is presented. These circuits combine features from both complementary CMOS and pass gates architectures. The simulation results using a 0.7 μm technology show that circuits synthesized according to the proposed method may achieve significant improvements in terms of area, power and delay over traditional full swing pass transistor logic and complementary CMOS.
Keywords :
CMOS logic circuits; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; minimisation of switching nets; 0.7 micron; Karnaugh map minimisation; area reduction; complementary CMOS gates architecture; delay reduction; high speed CMOS circuits; hybrid pass gate circuits; low power CMOS circuits; pass gates architecture; pass transistor synthesis method; power reduction; CMOS logic circuits; Circuit synthesis; Educational institutions; Energy consumption; Logic circuits; Logic gates; MOS devices; MOSFETs; Microelectronics; Page description languages;
Conference_Titel :
Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on
Print_ISBN :
1-58113-190-9
DOI :
10.1109/LPE.2000.155264
