An energy-efficient ternary interconnection link for asynchronous systems

Author

Philippe, Jean-Marc ; Kinvi-Boh, Ekué ; Pillement, Sébastien ; Sentieys, Olivier

Author_Institution

IRISA, Rennes Univ., Lannion

fYear

2006

fDate

21-24 May 2006

Lastpage

1014

Abstract

We introduce a new ternary link including a binary-to-ternary encoder and a ternary-to-binary decoder in voltage-mode multiple-valued logic (MVL). This link improves the transistor count compared to existing designs and it has no DC current path. The complete link was simulated with SPICE and a 0.13mum CMOS technology. It additionally shows interesting advantages on power consumption for global interconnects compared to full-swing signaling binary systems (up to 56.4% less energy consumption). Its low propagation delay is also an advantage in the design of high-speed on-chip links for asynchronous systems

Keywords

CMOS integrated circuits; SPICE; asynchronous circuits; integrated circuit interconnections; multivalued logic circuits; ternary logic; 0.13 micron; CMOS technology; SPICE; asynchronous systems; binary-to-ternary encoder; full-swing signaling binary systems; high-speed on-chip links design; power consumption; propagation delay; ternary interconnection link; ternary-to-binary decoder; voltage-mode multiple-valued logic; CMOS logic circuits; CMOS technology; Decoding; Energy consumption; Energy efficiency; Multivalued logic; Power system interconnection; Propagation delay; SPICE; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692759

Filename

1692759