Title :
A delay minimization router: (TD)2 router
Author :
Baba, Katsutoshi ; Tsujii, Naofumi ; Yamamoto, Katsuya ; Tsukiyama, Shuji
Author_Institution :
Dept. of Electr. & Electron. Eng., Chuo Univ., Tokyo, Japan
Abstract :
Since the interconnect delay has become the dominating factor in circuit performance, demands for a good delay-minimization router are very high. In this paper, we propose an algorithm to find a routing tree of a net which minimizes a total weighted delay τ to all sinks (input terminals), where the weight assigned to a sink represents a criticality of the delay to the sink. The algorithm uses top-down manner in determining the routing tree. Namely, the routing tree is determined from source (output terminal) to sinks. We also show experimental results to evaluate the performance of the proposed algorithm
Keywords :
circuit layout CAD; delays; integrated circuit layout; minimisation; network routing; (TD)2 router; delay minimization router; interconnect delay; routing tree; top-down manner; total weighted delay; Capacitance; Circuit optimization; Circuit topology; Delay estimation; Integrated circuit interconnections; Logic devices; Minimization; Routing; Timing; Wire;
Conference_Titel :
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location :
Chiangmai
Print_ISBN :
0-7803-5146-0
DOI :
10.1109/APCCAS.1998.743672
