DocumentCode
2533629
Title
A low-voltage CMOS multiplier for RF applications
Author
Debono, Carl James ; Maloberti, Franco ; Micallef, Joseph
Author_Institution
Dept. of Electron., Pavia Univ., Italy
fYear
2000
fDate
2000
Firstpage
225
Lastpage
227
Abstract
A low-voltage analog multiplier operating at 1.2 V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit was designed using standard 0.6 μm CMOS technology. Simulation results indicate an IP3 of 4.9 dBm and a spur free dynamic range of 45 dB.
Keywords
CMOS analogue integrated circuits; analogue multipliers; low-power electronics; 0.6 micron; 1.2 V; IP3; MOS transistors; analog multiplier; low-voltage CMOS multiplier; quadratic relation; saturation region; spur free dynamic range; Adders; Batteries; CMOS technology; Circuit simulation; Dynamic range; MOSFETs; Permission; Radio frequency; Resistors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on
Print_ISBN
1-58113-190-9
Type
conf
DOI
10.1109/LPE.2000.155285
Filename
876789
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