DocumentCode
2533686
Title
Hypernode reduction modulo scheduling
Author
Llosa, Josep ; Valero, Mateo ; Ayguadé, Eduard ; González, Antonio
Author_Institution
Dept. d´´Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
fYear
1995
fDate
29 Nov-1 Dec 1995
Firstpage
350
Lastpage
360
Abstract
Software pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. Most prior scheduling research has focused on achieving minimum execution time, without regarding register requirements. Most strategies tend to stretch operand lifetimes because they schedule some operations too early or too late. The paper presents a novel strategy that simultaneously schedules some operations late and other operations early, minimizing all the stretchable dependencies and therefore reducing the registers required by the loop. The key of this strategy is a pre-ordering that selects the order in which the operations will be scheduled. The results show that the method described in this paper performs better than other heuristic methods and almost as well as a linear programming method but requiring much less time to produce the schedules
Keywords
instruction sets; linear programming; pipeline processing; processor scheduling; resource allocation; hypernode reduction modulo scheduling; linear programming; loop scheduling technique; operand lifetimes; parallelism extraction; register requirements; software pipelining; stretchable dependencies; Concurrent computing; Human resource management; Linear programming; NP-complete problem; Optimal scheduling; Parallel processing; Performance evaluation; Pipeline processing; Processor scheduling; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture, 1995., Proceedings of the 28th Annual International Symposium on
Conference_Location
Ann Arbor, MI
ISSN
1072-4451
Print_ISBN
0-8186-7349-4
Type
conf
DOI
10.1109/MICRO.1995.476844
Filename
476844
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