• DocumentCode
    2533687
  • Title

    A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems

  • Author

    Hansen, John ; Singh, Montek

  • Author_Institution
    Univ. of North Carolina at Chapel Hill, Chapel Hill, NC, USA
  • fYear
    2010
  • fDate
    3-6 May 2010
  • Firstpage
    107
  • Lastpage
    116
  • Abstract
    In this paper, we address the problem of scheduling and allocation for asynchronous systems, and present methods for performing both area-constrained and time-constrained design space exploration. Much of the recent work in this area has been adapted from synchronous approaches, and thereby suffers from the drawback of assuming discrete time (or a discrete approximation). Further, most existing approaches are based on ILP methods, which can suffer from long solution search times for even modest-sized examples.We present instead an approach that does not assume or approximate timing as discrete, and is therefore able to find more optimal solutions for asynchronous systems. The scheduling approach uses a branch-and-bound search strategy with simple, effective heuristics to safely prune the search space, while guaranteeing an optimal solution. In particular, a high-quality initial solution is obtained heuristically, allowing the search space and overall search time to be significantly reduced, particularly when compared to ILP approaches. A 1.9x-180x improvement in run-time is achieved for small examples, and an improvement of multiple orders of magnitude for larger examples (including an example containing over a thousand operations).
  • Keywords
    asynchronous circuits; high level synthesis; integer programming; linear programming; scheduling; tree searching; ILP methods; area constrained design space exploration; asynchronous systems; branch-and-bound approach; high level synthesis; scheduling; search strategy; time constrained design space exploration; Asynchronous circuits; Genetic algorithms; High level synthesis; Optimal scheduling; Resource management; Runtime; Simulated annealing; Space exploration; Timing; USA Councils; allocation; asynchronous; branch-and-bound; high-level synthesis; scheduling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asynchronous Circuits and Systems (ASYNC), 2010 IEEE Symposium on
  • Conference_Location
    Grenoble
  • ISSN
    1522-8681
  • Print_ISBN
    978-0-7695-4032-0
  • Electronic_ISBN
    1522-8681
  • Type

    conf

  • DOI
    10.1109/ASYNC.2010.14
  • Filename
    5476974