Energy-efficient code generation for DSP56000 family

Author

Udayanarayanan, Sathishkumar ; Chakrabarti, Chaitali

Author_Institution

Dept. of Electr. Eng., Centre for Low Power Electron., Tempe, AZ, USA

fYear

2000

fDate

2000

Firstpage

247

Lastpage

249

Abstract

This paper presents a procedure to generate energy-efficient code for the Motorola DSP56K processor based on increasing the packing efficiency and minimizing the number of address instructions. The key features are a novel scheduling algorithm that reduces the dependencies between instructions, a register allocation algorithm that spills variables based on their packability, and an address code generation algorithm that minimizes the number of additional instructions. The size of the code generated by this procedure is on the average 45% (25%) smaller than that generated by Motorola´s g56 K (SPAM).

Keywords

digital signal processing chips; embedded systems; instruction sets; scheduling; DSP56000 family; Motorola DSP56K processor; address code generation algorithm; address instructions; energy-efficient code generation; packability; packing efficiency; register allocation algorithm; scheduling algorithm; Digital signal processing; Energy efficiency; Low power electronics; Permission; Power generation; Processor scheduling; Registers; Scheduling algorithm; Signal processing algorithms; Unsolicited electronic mail;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on

Print_ISBN

1-58113-190-9

Type

conf

DOI

10.1109/LPE.2000.155292

Filename

876796