• DocumentCode
    2533846
  • Title

    Concurrency Reduction of Untimed Latch Protocols - Theory and Practice

  • Author

    Varanasi, Santosh N. ; Stevens, Kenneth S. ; Birtwistle, Graham

  • Author_Institution
    Electr. & Comput. Eng., Univ. of Utah, Salt Lake City, UT, USA
  • fYear
    2010
  • fDate
    3-6 May 2010
  • Firstpage
    26
  • Lastpage
    37
  • Abstract
    A systematic investigation into concurrency reduction of untimed asynchronous 4-phase latch controllers is reported. Starting with a state graph that exhibits maximal concurrency, rules are provided for systematically reducing its states and thereby curtailing its behaviors. The rules predict liveness and occupancy, as well as the regularity and behavior of their pipelines. The rules also reveal the precise extent of the design space and thus provide a secure platform on which to study the implications of concurrency reduction on power, performance and area by implementing and evaluating the complete set of abstracted controllers. This complete characterization enhances the understanding and usage of concurrency and its reduction in handshake protocols. Trade-offs have been observed and reported which will aid designers in trying to find the best protocols for a required specification. Finally, the best synthesized protocols in this class have been identified.
  • Keywords
    asynchronous circuits; concurrency control; flip-flops; formal specification; protocols; security of data; synchronisation; concurrency reduction; handshake protocols; liveness prediction; occupancy prediction; required specification; secure platform; state graph; untimed asynchronous 4-phase latch controllers; untimed latch protocols; Asynchronous circuits; Computer science; Concurrent computing; Control systems; Decoding; Latches; Microprocessors; Pipeline processing; Protocols; Signal design; Asynchronous Design; Concurrency Reduction; Synchronization; pipelining; protocols; verification;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asynchronous Circuits and Systems (ASYNC), 2010 IEEE Symposium on
  • Conference_Location
    Grenoble
  • ISSN
    1522-8681
  • Print_ISBN
    978-0-7695-4032-0
  • Electronic_ISBN
    1522-8681
  • Type

    conf

  • DOI
    10.1109/ASYNC.2010.13
  • Filename
    5476994