Analysis and design of low-phase-noise ring oscillators

Author

Dai, Liang ; Harjani, Ramesh

Author_Institution

Minnesota Univ., Minneapolis, MN, USA

fYear

2000

fDate

2000

Firstpage

289

Lastpage

294

Abstract

This paper presents a framework for CMOS ring oscillator phase noise analysis for given power consumption specifications. This model considers both linear and nonlinear operations. It indicates that fast rail-to-rail switching has to be achieved for low phase noise and that the up-conversion of low-frequency noise from the current bias/control circuit can be significant. Our phase noise model is validated via simulation and measurement results. We also present a coupled-ring oscillator whose phase noise is -114 dBc/Hz at a 600 kHz offset from the 960 MHz carrier frequency.

Keywords

CMOS integrated circuits; UHF integrated circuits; UHF oscillators; integrated circuit noise; network analysis; phase noise; voltage-controlled oscillators; 960 MHz; CMOS ring oscillator; LF noise up-conversion; coupled-ring oscillator; current bias/control circuit; fast rail-to-rail switching; linear operation; low-frequency noise; low-phase-noise ring oscillators; nonlinear operation; phase noise analysis; phase noise model; power consumption specifications; Circuit simulation; Coupling circuits; Energy consumption; Low-frequency noise; Noise measurement; Phase measurement; Phase noise; Ring oscillators; Semiconductor device modeling; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on

Print_ISBN

1-58113-190-9

Type

conf

DOI

10.1109/LPE.2000.155301

Filename

876805