Title :
Skip the Analysis: Self-Optimising Networks-on-Chip (Invited Paper)
Author :
Hollis, Simon J. ; Jackson, Chris
Author_Institution :
Dept. of Comput. Sci., Univ. of Bristol, Bristol, UK
Abstract :
In this paper, we investigate how the need for static analysis of data flowing through Networks-on-Chip in many-core and SoC systems may be eliminated, yet still allow network optimisations to improve runtime behaviour. Our approach is to replace a priori static analysis with run-time optimisations, taking place in the network itself. To do this, we introduce our self-optimising NoC topology: Skip-links, which inserts long-range links into a standard mesh. We evaluate the performance of Skip-links at run-time against the optimal configuration, as determined by static analysis, for both the transpose and tornado traffic patterns. We show that the local decision-making algorithm employed by Skip-links comes close to optimum, carrying 70% of theoretical maximum traffic flows for tornado traffic, and reducing average hop counts by 18% for transpose traffic.
Keywords :
multiprocessing systems; network routing; network-on-chip; Skip-links; long-range links; many-core systems; network optimisations; runtime behaviour; self-optimising networks-on-chip; tornado traffic patterns; transpose traffic patterns; Algorithm design and analysis; Heuristic algorithms; Network topology; Optimization; Routing; Topology; Tornadoes; Long-range Links; Network-on-Chip; NoC; Skip-links; dynamic optimisation; static analysis;
Conference_Titel :
Electronic System Design (ISED), 2010 International Symposium on
Conference_Location :
Bhubaneswar
Print_ISBN :
978-1-4244-8979-4
Electronic_ISBN :
978-0-7695-4294-2
DOI :
10.1109/ISED.2010.12