Title :
Reliable low-power design in the presence of deep submicron noise
Author :
Shanbhag, Naresh ; Soumyanath, K. ; Martin, Samuel
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
Scaling of feature sizes in semiconductor technology has been responsible for increasingly higher computational capacity of silicon. This has been the driver for the revolution in communications and computing. However, questions regarding the limits of scaling (and hence Moore´s Law) have arisen in recent years due to the emergence of deep submicron noise. This paper describes noise in deep submicron CMOS and its impact on digital as well as analog circuits. In particular, noise-tolerance is proposed as an effective means for achieving energy and performance efficiency in the presence of DSM noise.
Keywords :
CMOS analogue integrated circuits; CMOS digital integrated circuits; CMOS integrated circuits; VLSI; high-speed integrated circuits; integrated circuit design; integrated circuit noise; integrated circuit reliability; low-power electronics; DSM noise; analog circuits; deep submicron CMOS; deep submicron noise; digital circuits; noise tolerant VLSI; reliable low-power design; Circuit noise; Crosstalk; Driver circuits; Energy efficiency; Integrated circuit reliability; Integrated circuit technology; Moore´s Law; Noise level; Power system reliability; Semiconductor device noise;
Conference_Titel :
Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on
Print_ISBN :
1-58113-190-9
DOI :
10.1109/LPE.2000.155302
