Relaxed tree search MIMO signal detection algorithm design and VLSI implementation

This paper presents an implementation-oriented breadth-first tree search MIMO detector design solution. Techniques at algorithm and VLSI architecture levels are developed to improve the implementation efficiency. Using Synopsys synthesis tool with 0.13 mum CMOS technology, we designed soft-output detectors for 4 times 4 MIMO channel with 64-QAM modulation. With the silicon areas less than 15 mm ², the detectors can achieve up to about 80 Mbps and realize the performance very close to detectors using the sphere decoding algorithm