Energy Efficient and Process Tolerant Full Adder Design in Near Threshold Region Using FinFET

This paper investigates a robust 1-bit static full adder using FinFET at near-threshold region (NTR), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region provides minimum-energy point for the different frequency of operation with more favorable performance and variability characteristics. The proposed design features higher computing speed (by 4.49.×) and lower energy (by 3.90.× ) at the expense of 1.13.× higher power dissipation. The proposed design also offers 1.38× improvements in power variability, 2.19× improvements in delay variability and 2.41× improvement in power delay product (PDP) variability against process, voltage, and temperature (PVT) variations. The power, speed and energy evaluation has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 32nm Berkeley Predictive Technology Model (BPTM).