Abstract :
The paper deals with the following topics:formal logic; physical synthesis; low-power circuits; harvesting; synchronisers; high level synthesis; retiming; power-performance optimisation; arbitration; delay insensitivity; and GasP.
Keywords :
asynchronous circuits; electronic engineering computing; formal logic; formal verification; high level synthesis; low-power electronics; optimisation; synchronisation; GasP; arbitration; delay insensitivity; formal logic; harvesting; high level synthesis; low-power circuits; physical synthesis; power-performance optimisation; retiming; synchronisers;
Conference_Titel :
Asynchronous Circuits and Systems (ASYNC), 2010 IEEE Symposium on
Conference_Location :
Grenoble
Print_ISBN :
978-0-7695-4032-0
DOI :
10.1109/ASYNC.2010.1
