Energy Recovery Techniques for CNT-FET Circuits

Author

Srivastava, A. ; Xu, Y. ; Soundararajan, R.

Author_Institution

Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA

fYear

2010

fDate

20-22 Dec. 2010

Firstpage

81

Lastpage

84

Abstract

In this paper, utilization of energy recovery techniques in carbon nanotube field-effect transistor (CNT-FET) circuits is discussed. Four different energy recovery techniques for complementary on-chip CNT-FET XNOR/XOR circuits are extensively studied and simulated using Cadence^® Spectre simulator. The simulation results show that the power density of CNT-FET circuits is much higher than the maximum power density limit set by ITRS 2003. Among the four energy recovery circuits, new clocked adiabatic logic (CAL) type CNT-FET circuits exhibit the best performance.

Keywords

NOR circuits; carbon nanotubes; field effect transistor circuits; cadence spectre simulator; carbon nanotube field-effect transistor circuit; clocked adiabatic logic type CNT-FET circuit; energy recovery technique; on-chip CNT-FET XNOR-XOR circuit; power density; CMOS integrated circuits; Clocks; Integrated circuit modeling; Logic gates; Mathematical model; System-on-a-chip; Transistors; CNT-FET; CNT-FET Modeling; Carbon Nanotubes; Energy Recovery Techniques;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic System Design (ISED), 2010 International Symposium on

Conference_Location

Bhubaneswar

Print_ISBN

978-1-4244-8979-4

Electronic_ISBN

978-0-7695-4294-2

Type

conf

DOI

10.1109/ISED.2010.24

Filename

5715154