Phase sampling: a new approach to the design of LF direct digital frequency synthesizers

A direct digital frequency synthesizer (DDFS) is a circuit capable of producing programmable-frequency sinusoids from a reference clock signal. Its operation is based on a counter whose output serves as address to a ROM, from which voltage (or current) samples are retrieved at constant time intervals. The power and area demanded by the ROM constitute its main limitation. To circumvent it, we describe a time-domain (phase) sampling approach, in which the samples are taken at constant voltage (or current) intervals rather than at constant time intervals. The result is a system with a smaller ROM and a simpler DAC. The main drawback is the reduced maximum frequency attainable with this approach