Low-Cost Design of Serial-Parallel Multipliers Over GF(2^m) Using Hybrid Pass-Transistor Logic (PTL) and CMOS Logic

We have designed pass-transistor logic (PTL)-based D flip-flop and T flip-flop to be used in finite field multiplication. Since both CMOS and PTL have their respective advantages in area, speed, and power, we have compared two different designs (conventional implementation and improved implementation) of serial-parallel finite field multiplication using pure CMOS, pure PTL, and hybrid PTL/CMOS logic. Experimental results with UMC 90nm technology show that the improved architecture of finite field multiplication composed of PTL-based T flip-flops can substantially reduce the total area, delay and power. Furthermore, the proposed cell-based design flow with hybrid PTL/CMOS cell library can be used to generate any other combinational and sequential logic circuits.