A Novel Technology Mapping Technique for BDD-Based Circuits Using LEAP Cells

Library-based Pass Transistor Logic (PTL) synthesis, like Lean Integration with Pass-Transistors (LEAP) synthesis, has drawn significant attention to the VLSI research community. In this paper, we first propose a modified Y3 LEAP cell that was originally invented by K. Yano, Y. Sasaki, K. Rikino and K. Seki. Secondly we propose a new technology dependent mapping technique and compare the results with the existing methods published in and. Our technique yields a significant reduction in number of cells used in the core logic block and in other parameters like power, delay and power-delay-product.