A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs

In this paper, an algorithmically defined buffer and ring oscillator design for low energy applications is proposed. The goal of the algorithm is to easily converge to a low energy solution while the system maintains constant speed and full swing at a given supply voltage, irrespective of the capacitive load. The experimental circuit is a 980MHz oscillator operating from a 0.8V supply, driving a 1pF load, designed using a 0.18mum TSMC CMOS process technology. A comparison to the well known minimum delay tapered buffer, using an exponential horn designed independently of the oscillator, is done. The comparison shows that our algorithm produces a 3.7-3.9 times improvement in terms of power, energy, and energy delay product (EDP) metrics, and 14.6 times improvement in terms of the energy area product (EAP)