Analysis and design of MCML gates with hysteresis

Author

Alioto, M. ; Pancioni, L. ; Rocchi, S. ; Vignoli, V.

Author_Institution

Dipt. di Ingegneria dell´´Informazione, Univ. di Siena

fYear

2006

fDate

21-24 May 2006

Abstract

In this paper, hysteresis is exploited to improve the performance of positive feedback source coupled logic circuits, which are a modification of the traditional MOS current-mode logic (MCML) (Alioto, 2004). To understand the effect of hysteresis on the DC characteristics, a model of the noise margin is analytically derived. This model shows that hysteresis improves the noise margin, whose increase is traded-off to reduce the logic swing, which in turn can have a beneficial impact on the speed performance. Practical cases where hysteresis is advantageous are identified, and a comparison with PFSCL gates without hysteresis is carried out. Analysis shows that in such cases hysteresis significantly improves the speed performance and the power efficiency of PFSCL gates, which is a critical aspect in this kind of logic. Simulation results are presented based on a 0.18-mum CMOS process

Keywords

CMOS logic circuits; current-mode logic; hysteresis; integrated circuit noise; logic design; logic gates; 0.18 micron; CMOS process; MCML gates; MOS current-mode logic; PFSCL gates; hysteresis; logic swing; noise margin; positive feedback source coupled logic circuits; CMOS logic circuits; CMOS process; Circuit noise; Feedback circuits; Hysteresis; Logic circuits; Logic design; MOSFETs; Performance analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692822

Filename

1692822