Simplification of two-level logic circuit function by three-branch-tree-expansion and binary decision diagrams

Author

Goto, Kimio ; Ito, Takashi ; Chin, Kee Seng ; Ling, Xiao Ping

Author_Institution

Kanagawa Inst. of Technol., Japan

fYear

1998

fDate

24-27 Nov 1998

Firstpage

383

Lastpage

386

Abstract

This paper describes the generation of a minimal covering of prime implicants for either the single-output function or the multiple-output function having `don´t cares´ by using Three-Branch-Tree-Expansion (TBTE) method with the support of Binary Decision Diagrams (BDDs). This algorithm was realized in C language program and compared with ESPRESSO-II in terms of both the computation time and the number of prime implicants by using a SUN SPARC station 5. Our method recorded much shorter computation time than ESPRESSO-II, especially for the single-output function

Keywords

Boolean functions; binary decision diagrams; logic CAD; switching functions; BDD; C language program; SUN SPARC station 5; binary decision diagrams; computation time; logic circuit function simplification; multiple-output function; prime implicants; single-output function; three-branch-tree-expansion method; two-level logic circuit function; Binary decision diagrams; Boolean functions; Cities and towns; Data structures; Indium tin oxide; Joining processes; Logic circuits; Logic functions; Sun;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on

Conference_Location

Chiangmai

Print_ISBN

0-7803-5146-0

Type

conf

DOI

10.1109/APCCAS.1998.743784

Filename

743784