A simplicial CNN visual processor in 3D SOI-CMOS

Author

Mandolesi, Pablo S. ; Julian, Pedro ; Andreou, Andreas G.

Author_Institution

Departamento de Ingenieria Electrica y de Computadoras, Univ. Nacional del Sur, Bahia Blanca

fYear

2006

fDate

21-24 May 2006

Lastpage

1314

Abstract

This paper presents the architecture for a SIMD digital visual processor unit (VPU) that is based on the simplicial CNN (S-CNN) algorithm. The system is designed for three dimensional CMOS integration in the three tier MITLL 3D SOI-CMOS 0.18 mum technology. The architecture includes input/output sub-systems, in the third tier, arithmetic logic units (ALU) and register files on the third and second tiers and instruction cache memory and a timing state machine on the first tier. The partition of the architecture exploits its physical realization in three dimensional CMOS. Parallel optical data input through an array of photodetectors and analog interface circuits in the third tier facilitate testing and characterization

Keywords

CMOS integrated circuits; microcomputers; neural chips; parallel processing; silicon-on-insulator; 0.18 micron; 3D CMOS integration; ALU; MITLL 3D SOI-CMOS; S-CNN algorithm; SIMD; VPU; arithmetic logic units; digital visual processor unit; input/output sub-systems; instruction cache memory; photodetectors; register files; simplicial CNN; timing state machine; Arithmetic; CMOS logic circuits; CMOS technology; Cache memory; Cellular neural networks; Circuit testing; Optical arrays; Photodetectors; Registers; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692834

Filename

1692834