The hardware platform for the tests and evaluation of the airborne GNSS receiver algorithms

The main aim of this project is to show a concept of the hardware platform for evaluation of the GNSS receiver algorithms. There was a request for good flexibility of the system for designing elements of multiple GNSS receivers. Designed system is suitable for receiving a signal at chosen frequency from the operating range (915 to 2175 MHz) and its next processing. Front-end device receives the signal and does a QPSK demodulation. Platform is based on the FPGA, so the module structure of the implemented system allows good dealing with designed entities. Suitable is the possibility of simply designing and implementing the digital filters in this platform. Although used RF frontend MAX2120 is not directly intended for GPS signal receiving or processing, with its number of parameters it is convenient to utilize in this issue. Paper describes how the MAX2120 is tuned through I2C bus by I2C Master device implemented in used FPGA. For demonstration, there was implemented and tested the system that receives GPS signal, demodulates it and do the A/D conversion for next processing in the FPGA. There are designed multiple data filters and dealing with them in the end.