An analog VLSI time-delay neural network implementation for phoneme recognition

Author

Gatt, E. ; Micallef, J. ; Chilton, E.

Author_Institution

Dept. of Microelectron., Malta Univ., Msida, Malta

fYear

2000

fDate

2000

Firstpage

315

Lastpage

320

Abstract

The paper proposes an analog VLSI neural network chip, which can be cascaded in order to develop a time-delay neural network system for phoneme recognition. Backpropagation learning has been adopted to train the network to recognise phoneme frames extracted from the TIMIT database. A prototype chip, implemented using CMOS 2.0 μm, double metal, double poly technology is also described together with its specifications

Keywords

CMOS analogue integrated circuits; VLSI; backpropagation; neural chips; speech recognition; CMOS analog IC; TIMIT database; VLSI; backpropagation learning; double metal double poly; neural net chip; phoneme recognition; time-delay neural network; Backpropagation; Circuits; Databases; History; Information technology; Mathematics; Microelectronics; Neural networks; Prototypes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Cellular Neural Networks and Their Applications, 2000. (CNNA 2000). Proceedings of the 2000 6th IEEE International Workshop on

Conference_Location

Catania

Print_ISBN

0-7803-6344-2

Type

conf

DOI

10.1109/CNNA.2000.876864

Filename

876864

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2535085