Refined Si-CMOS-MEMS process using AOE, drie and preform bonding

This paper presents a Si-CMOS-MEMS fabrication process that forms released structures out of a 10 μm CMOS metal and oxide stack along with a 50 μm-thick section of the underlying silicon substrate. The process employs back-side silicon grinding that provides silicon mean roughness of 20 nm and maximum peak-to-valley roughness of 264 nm. The thinned MEMS substrate is bonded with solder preforms to a silicon base. Advanced Oxide Etch (AOE) of the CMOS MEMS stack has a rate of 527 nm/min and leaves no polymer residue. Three different thermal shunting methods during the silicon DRIE step are studied to alleviate isotropic silicon etch artifacts. Test of a Si-CMOS-MEMS crab-leg resonator validates the process. The device has a quality factor of 750 and resonant frequency of 36.4 kHz in air.