An on-chip combinational decompressor for reducing test data volume

Utilizing an on-chip decompressor is an efficient method to reduce test data volume in multiple-scan-chain designs. This paper investigates a new technique to implement the decompressor by combinational circuits. The proposed architecture drives a large number of internal scan chains with far fewer external input pins, thus delivering significant reductions in test data volume. Based on the analysis of compatible relationships among scan slices, the number of external scan inputs can be minimized. The effectiveness and applicability of the proposed scheme are demonstrated by experimental results