Title :
Hierarchical exploration and selection of transistor-topologies for analog circuit design
Author :
Wang, Xiaoying ; Hedrich, Lars
Author_Institution :
Dept. of Comput. Sci., Frankfurt Univ.
Abstract :
This paper presents a method of design automation for analog circuits, focusing on topology generation and quick performance evaluation. First we describe a new mechanism to generate circuit topologies with hierarchical blocks, which are specialized by additional terminal information. The connection between blocks is in compliance with a set of synthesis rules, which are extracted from typical schematics in the literature. Fast symbolic analysis of linear performances is used to select appropriate topologies quickly. Finally, the selected topologies can be sized by an external sizing tool. Experimental results show the creativity and efficiency of our method
Keywords :
analogue circuits; network topology; transistor circuits; analog circuit design; design automation; external sizing tool; fast symbolic analysis; quick performance evaluation; transistor topologies; Analog circuits; Blades; Circuit synthesis; Circuit topology; Computer science; Design automation; Impedance; Mirrors; Performance analysis; Signal synthesis;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692873
