Die-level TSV fabrication platform for CMOS-MEMS integration

This paper reports a new post-CMOS processing platform for die-level through-silicon-via (TSV) fabrication, based on wafer reconstitution from embedded dies, parylene deposition, stencil lithography, and bottom-up electroplating. The goal of this work is to develop a heterogeneous 3D-integration technique for the applications requiring CMOS-MEMS integration with medium-density vertical interconnections, without using any optical alignment and photolithography step. With the combination of the proposed techniques, TSV aspect-ratios higher than 6:1 are demonstrated on dummy chips. The paper also presents the die-to-carrier-wafer alignment tests showing 5μm of average alignment error by manual pick and placement of dies.