Bit level architectural exploration technique for the design of low power multipliers

In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low power consumption. While this ideas is applicable to array multipliers, the reduced area of the Wallace tree multiplier is a temptation for the designer. Therefore, a mixed architecture, using both traditional and bypass techniques is proposed, which outperforms the Wallace tree in both power consumption and timing, with a 15%-20% extra area penalty