• DocumentCode
    2536060
  • Title

    Matrix-vector multiplier module for natural/synthetic hybrid video coding

  • Author

    Fujishima, Hideyuki ; Takemoto, Yusuke ; Onoye, Takao ; Shirakawa, Isao ; Matsumura, Keriji

  • Author_Institution
    Graduate Sch. of Eng., Osaka Univ., Japan
  • fYear
    1998
  • fDate
    24-27 Nov 1998
  • Firstpage
    631
  • Lastpage
    634
  • Abstract
    An architecture of a Matrix-Vector Multiplier (MVM) is devised, which is dedicated to MPEG-4 natural/synthetic video decoding. The MVM can perform the matrix-vector multiplication both in the IDCT (Inverse Discrete Cosine Transform) and in the geometrical transformation of 3D CG; or specifically, can achieve the multiplication of a 4×4-matrix by a 4-tuple vector necessary both in the 1D IDCT for eight pixels and in the geometrical transformation for a point in a 3D space. The present paper describes a new architecture of this MVM, and also shows the implementation result of a functional module composed of four MVMs with the use of 440 K transistors, which can operate at 20 MHz or less
  • Keywords
    VLSI; decoding; digital arithmetic; digital signal processing chips; discrete cosine transforms; matrix multiplication; multiplying circuits; video coding; IDCT; MPEG-4 video decoding; discrete cosine transform; geometrical transformation; inverse DCT; matrix-vector multiplier module; natural/synthetic hybrid video coding; Character generation; Computer displays; Decoding; Discrete cosine transforms; Hardware; Laboratories; MPEG 4 Standard; Matrix decomposition; Video coding; Video sharing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
  • Conference_Location
    Chiangmai
  • Print_ISBN
    0-7803-5146-0
  • Type

    conf

  • DOI
    10.1109/APCCAS.1998.743899
  • Filename
    743899