• DocumentCode
    2536154
  • Title

    A fault-tolerant architecture for nanoelectronic signal processing

  • Author

    Fujisaka, Hisato ; Hamano, Daisuke ; Kamio, Takeshi ; Sakamoto, Masahiro

  • Author_Institution
    Fac. of Inf. Sci., Hiroshima Univ., Japan
  • fYear
    2004
  • fDate
    16-19 Aug. 2004
  • Firstpage
    586
  • Lastpage
    588
  • Abstract
    A fault-tolerant system architecture is proposed for digital signal processing with quantum devices which make transient errors. Two techniques are employed in the proposed architecture. Firstly, there exists no circuit block to control system operation sequence. Every circuit modules in the system autonomously repeat simple operation at each clock cycle. This structure prevents system failures. Secondly, pulse density modulated single-bit data whose average represents signal level is the data form for the system. Unlike multi-bit binary data, a few bit-errors do not make data haphazard but merely let data lower in accuracy. Computer simulation of a digital filter based on the architecture demonstrated the effectiveness of these techniques.
  • Keywords
    digital filters; digital signal processing chips; digital simulation; error statistics; fault tolerance; nanoelectronics; bit error rate; circuit modules; clock cycle; computer simulation; control system operation; digital filter; digital signal processing; fault tolerant system architecture; nanoelectronic signal processing; pulse density modulated single-bit data; quantum devices; transient errors; Circuits; Clocks; Computer simulation; Control systems; Digital filters; Digital signal processing; Fault tolerance; Fault tolerant systems; Pulse modulation; Signal processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology, 2004. 4th IEEE Conference on
  • Print_ISBN
    0-7803-8536-5
  • Type

    conf

  • DOI
    10.1109/NANO.2004.1392428
  • Filename
    1392428