A high-speed of self-timing carry-completion for direct two´s complement multipliers

An algorithm of a new design for an asynchronous self-timing carry-completion adder is presented. This new type adder can be used for the last stage of carry-sum addition in the direct two´s complement multiplier. The execution time of an n×n multiplication is expected to improve to log₂(n/2-1) cycles instead of (2n-1) cycles, while the hardware is still kept at the same complexity as the conventional carry-save multipliers. A further improvement can be expected by using this method on on-the-fly scheme in parallel for fast multiplication without carry-propagate addition. Several types of these asynchronous self-timing carry-completion adders are analyzed and compared. An optimal type is selected incorporated within the two´s complement multiplier, so that minimum execution time of multiplication and simplest hardware are reached