Title :
A broadcast-based test scheme for reducing test size and application time
Author :
Rau, Jiann-Chyi ; Chang, Jun-Yi ; Chen, Chien-Shiun
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Taipei
Abstract :
We present efficient method for reducing test application time by broadcasting test configuration. We compare our method based on single, multiple, 1-1 in-order mapping, even distribution, nearest signal probability matching, and in-order pseudo-exhaustive method. The results of our experiments indicate that our method reducing the test pattern number and the test application time by running the ATPG tool provided by SIS
Keywords :
VLSI; automatic test pattern generation; integrated circuit testing; VLSI; automatic test pattern generation; broadcasting test configuration; test application time reduction; Automatic test pattern generation; Benchmark testing; Broadcasting; Circuit testing; Electrical fault detection; Fault detection; Flip-flops; Pins; Signal mapping; Test pattern generators; BIST; Test Application Time; Test Size; Testing; VLSI;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692902
