DocumentCode
2536479
Title
On nanoelectronic architectural challenges and solutions
Author
Beiu, Valeriu ; Rückert, Ulrich ; Roy, Sandip ; Nyathi, Jabulani
Author_Institution
Sch. of EE&CS, Washington State Univ., Pullman, WA, USA
fYear
2004
fDate
16-19 Aug. 2004
Firstpage
628
Lastpage
631
Abstract
This paper discusses the many challenges in the design of future nano architectures that result from the use of nanoelectronic devices. The relations among these challenges are studied, and an unfortunately subjective relative ranking is proposed. Possible solutions are suggested.
Keywords
integrated circuit design; nanoelectronics; integrated circuit; nanoelectronic architectural challenges; nanoelectronic devices; Algorithm design and analysis; Computer architecture; Design optimization; Logic testing; Neural nanotechnology; Redundancy; Semiconductor devices; Space heating; Stochastic processes; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanotechnology, 2004. 4th IEEE Conference on
Print_ISBN
0-7803-8536-5
Type
conf
DOI
10.1109/NANO.2004.1392441
Filename
1392441
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