A novel VLSI design for Ziv-Lempel data compression

In this paper, we present a simple real-time parallel architecture for CMOS VLSI implementation of Ziv-Lempel (LZ type) data compression system. This encoding system employs a linear systolic array to find concurrently the matches between each input data character and its corresponding dictionary. A new encoding architecture is proposed to improve the encoding speed and reduce the hardware complexity for the encoding cells. The access time of memory is reduced to save its power consumption for high-speed applications. The encoder encodes one character( more than 8 bits) per encoding cycle. The clock rate by Verilog simulator can be constrained below 12 ns by 0.6 μm CMOS technology process