A new high logic density FPGA for bit-serial pipeline datapath

In this paper, we present our work on the design of a new FPGA architecture targeted at a high-performance bit-serial pipeline datapath. Bit-parallel systems introduce a large routing area overhead which is especially critical in using FPGAs, where the device utilization and operation frequency become low because of the large routing penalty. Here we propose a new FPGA architecture for high-performance bit-serial pipeline datapaths, which are very efficiency in routing. Our new FPGA guarantees near 100% logic utilization with a straightforward place and route tool due to high routability of bit-serial circuits and simple routing interconnect architecture