DocumentCode
2536809
Title
Measurement of glitches based on variable gate delay model using VHDL simulator
Author
Seko, Tadashi ; Nakamura, A. ; Kikuno, Tohru
Author_Institution
Nara Nat. Coll. of Technol., Japan
fYear
1998
fDate
24-27 Nov 1998
Firstpage
767
Lastpage
770
Abstract
In this paper we propose a new method to measure the number of glitches of a circuit based on variable gate delay model, and then develop the VHDL simulator augmented with an evaluator which implements the proposed method. The application to adders and multipliers shows the usefulness of the proposed method
Keywords
adders; circuit simulation; delay estimation; digital integrated circuits; hardware description languages; integrated circuit testing; logic testing; multiplying circuits; VHDL simulator; adders; evaluator; glitches measurement; multipliers; variable gate delay model; Adders; Circuit simulation; Clocks; Delay; Educational institutions; Electronic mail; Logic; Power dissipation; Semiconductor device modeling; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location
Chiangmai
Print_ISBN
0-7803-5146-0
Type
conf
DOI
10.1109/APCCAS.1998.743934
Filename
743934
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