DocumentCode
2536876
Title
Hierarchical redundancy design for WSI neuro-processors
Author
Tomabechi, Nobuhiro
Author_Institution
Hachinohe Inst. of Technol., Japan
fYear
1998
fDate
24-27 Nov 1998
Firstpage
787
Lastpage
790
Abstract
This paper proposes the hierarchical redundancy design for the defect recovery of wafer scale neuro-processors. The design combines both the circuit level redundancy and the system level redundancy. The hierarchical redundancy design results in that a neuro-processor composed of 500 neurons may be implemented on a single wafer with 27% increase of hardware and with sufficient yield
Keywords
integrated circuit design; integrated circuit reliability; integrated circuit yield; neural chips; redundancy; wafer-scale integration; WSI neuroprocessors; circuit level redundancy; defect recovery; hierarchical redundancy design; system level redundancy; wafer scale neuroprocessors; yield; Adders; Binary trees; Circuits; Digital signal processing; Hardware; Neural networks; Neurons; Process design; Production; Robot control;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location
Chiangmai
Print_ISBN
0-7803-5146-0
Type
conf
DOI
10.1109/APCCAS.1998.743939
Filename
743939
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