Low-power implementation of FIR filters within an adaptive reconfigurable architecture

This paper presents a custom very-large-scale-integration architecture, which consists of a reconfigurable hardware substrate and a hybrid-genetic algorithm responsible for resolving the optimal configuration for the reconfigurable components of the substrate. The reconfigurable hardware is specifically tailored for the implementation of multiplier-less symmetrical finite-impulse-response filters based on the primitive operator technique, while the architecture of the hybrid-genetic algorithm aims to improving the quality of the realized filters and speeding-up the time required for their realization. Power analysis demonstrates that the filters, which are implemented by our architecture, consume considerably less power than industrial field-programmable-gate-arrays, targeting similar applications