Title :
All-Digital Phase-Locked Loop for Optical Interconnect Applications
Author :
Hieu, Ngo Trong ; Lee, Tae-Woo ; Park, Hyo-Hoon
Author_Institution :
Opt. Interconnection & Switching Lab., Inf. & Commun. Univ., Daejeon
Abstract :
A novel all-digital phase-locked loop (ADPLL) is proposed and designed for chip-to-chip optical interconnect applications. The ADPLL is designed using the TSMC 0.18 mum CMOS technology. The core size of the ADPLL is 550times1040 mum2. The frequency range of the ADPLL is 3.0 - 3.4 GHz and power consumption is 18.67 mA with 1.8 V supply voltage.
Keywords :
CMOS integrated circuits; digital phase locked loops; integrated optics; integrated optoelectronics; optical interconnections; 1.8 V; 18.67 mA; 3 to 3.4 GHz; CMOS technology; TSMC; all-digital phase-locked loop; chip-to-chip optical interconnect applications; CMOS technology; Clocks; Counting circuits; Energy consumption; Optical interconnections; Optical receivers; Phase frequency detector; Phase locked loops; Signal generators; Voltage; ADPLL; DCO; PFD; PLL; clock recovery; optical interconnection;
Conference_Titel :
Advanced Communication Technology, The 9th International Conference on
Conference_Location :
Gangwon-Do
Print_ISBN :
978-89-5519-131-8
DOI :
10.1109/ICACT.2007.358726
