Implementation of space-efficient voltage-insensitive capacitances in integrated circuits

In this paper, an approach of implementing voltage-insensitive and space-efficient capacitances has been proposed. It tackles capacitive elements related to the thin dielectric layers available in fabrication technologies of integrated circuits. It makes the use of the voltage-independent ones, such as the overlap capacitances of MOS transistors, and the voltage-dependency of the capacitances attached to the same circuit nodes are minimized by device geometric sizing and voltage biasing. In the case of using the MOS transistor gate dielectric layer, the capacitance is scaled by the width of the gate area of the transistor employed. As the transistor feature size is of sub-micron, the unit capacitance can be very small and the capacitances can be scaled easily and precisely, which facilitates a significant down-scale of the circuit geometric dimension, operation delay and, at the same time, power dissipation. As an example of application of the proposed approach, a charge-mode parallel D/A converter is proposed in this paper