A 20-MS/s sigma delta modulator for 802.11a applications

Author

Chiang, Jen-Shiun ; Li, Yi-Tsung ; Chen, Hsin-Liang

Author_Institution

Dept. of Electr. Eng., Tamkang Univ., Taipei

fYear

2006

fDate

21-24 May 2006

Abstract

In this paper, a 20-Msample/sec and 12-bit resolution sigma delta modulator for 802.11a applications is presented. The distributed feedback with a forward input and resonator feedback schemes are utilized to implement this modulator. The fifth-order 3-bit quantizer single-loop sigma delta modulator achieves 20-MS/s conversion ratio with 74dB of dynamic range and 70dB of peak signal-to-noise-distortion ratio. The circuit is implemented in a standard 0.18 mum 1P6M CMOS technology. The core area is 0.77mm² (1.1 mm times 0.7mm) and the power consumption is only 38-mW at 1.8-V supply

Keywords

CMOS integrated circuits; IEEE standards; circuit feedback; sigma-delta modulation; wireless LAN; 0.18 micron; 0.7 mm; 1.1 mm; 1.8 V; 12 bit; 12-bit resolution sigma delta modulator; 1P6M CMOS technology; 3 bit; 38 mW; IEEE 802.11a; distributed feedback; fifth-order 3-bit quantizer single-loop sigma delta modulator; signal-to-noise-distortion ratio; Bandwidth; CMOS technology; Circuit simulation; Delta modulation; Delta-sigma modulation; Dynamic range; Feedback; Quantization; Transfer functions; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692978

Filename

1692978