A performance-aware IP core design for multimode transform coding using scalable-DA algorithm

Author

Chen, Jia-Wei ; Chen, Kuan-Hung ; Wang, Jinn-Shyan ; Guo, Jiun-In

Author_Institution

Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chia-Yi

fYear

2006

fDate

21-24 May 2006

Abstract

This paper proposes a performance-aware transform IP design which can be configured to appropriate hardware for different performance requirements on demand without requiring additional data bandwidth in multimode video coding (JPEG/MPEG-1/2/4/H.261/H.263/H.264). Based on the scalable-DA approach, three schemes of hardware configurations which are respectively composed of 3, 6, and 12 data-paths are illustrated. The three schemes of the proposed performance-aware DCT/IDCT can achieve CIF, 720HD, and digital cinema video formats when operated at 9.13 MHz, 41.48 MHz, and 188.75 MHz, respectively

Keywords

data compression; discrete cosine transforms; transform coding; video coding; 188.75 MHz; 41.48 MHz; 720HD; 9.13 MHz; CIF; DCT; H.261 video coding; H.263 video coding; H.264 video coding; IDCT; IP core design; JPEG; MPEG; data-paths; digital cinema video; hardware configurations; multimode transform coding; multimode video coding; scalable-DA algorithm; Algorithm design and analysis; Bandwidth; CMOS technology; Computer architecture; Discrete cosine transforms; Hardware; Motion pictures; Throughput; Transform coding; Video on demand;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692982

Filename

1692982