DocumentCode :
2538069
Title :
Realization and optimization of DSP based H.264 encoder
Author :
Wei, Zhe ; Cai, Canhui
Author_Institution :
Inst. of Inf. Sci. & Eng., Huaqiao Univ., Quanzhou
fYear :
2006
fDate :
21-24 May 2006
Abstract :
H.264 is a very efficient video compression standard. In this paper, a scheme of H.264 encoder implementation based on TMS320C6416 DSP is presented. The structure hardware, the developing platform, the procedure of code immigration and many optimizing methods are discussed. The optimization based on the extended instruction set of C64x for the critical time consuming modules, the scheduling of data rolled-in and rolled-out, and the exploitation of the limited on-chip storage resources are studied in detail to accelerate encoding speed. The experiment results have shown that the proposed H.264 encoder can encode QCIF image sequences in real-time speed with high image quality and compression efficiency. The proposed H.264 encoder can be employed in many real-time applications
Keywords :
data compression; digital signal processing chips; image sequences; video coding; H.264 encoder; QCIF image sequences; TMS320C6416 DSP; code immigration; extended instruction set; image compression; image quality; on-chip storage resources; video compression standard; Carbon capture and storage; Digital signal processing; Digital signal processing chips; Hardware; Image coding; Image sequences; Job shop scheduling; VLIW; Video compression; Virtual colonoscopy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
Type :
conf
DOI :
10.1109/ISCAS.2006.1692986
Filename :
1692986
Link To Document :
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