30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D

Author

Yang-Kyu Choi ; Yoo-Chan Jeon ; Ranade, P. ; Takenuchi, H. ; Tsu-Jae King ; Bokor, J. ; Chenming Hu

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

2000

fDate

19-21 June 2000

Firstpage

23

Lastpage

24

Abstract

MOSFETs with selectively deposited Ge raised source/drain (S/D) implemented in 8 nm ultra-thin-body (UTB) SOI are demonstrated. The Ge is selectively deposited by LPCVD and annealed at a low temperature using RTA (650/spl deg/C, 20 s). Devices with gate lengths down to 30 nm are obtained with 8 nm UTB and show excellent short-channel behavior.

Keywords

MOSFET; chemical vapour deposition; elemental semiconductors; germanium; rapid thermal annealing; semiconductor device measurement; silicon-on-insulator; Ge selective LPCVD; Ge-Si-SiO/sub 2/; MOSFETs; RTA; UTB SOI; anneal temperature; gate length; selectively deposited Ge raised S/D; selectively deposited Ge raised source/drain; short-channel behavior; ultra-thin-body SOI; ultra-thin-body SOI MOSFET; Annealing; Dry etching; Fabrication; Fluctuations; Immune system; MOSFET circuits; Parasitic capacitance; Silicon on insulator technology; Thermal resistance; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference, 2000. Conference Digest. 58th DRC

Conference_Location

Denver, CO, USA

Print_ISBN

0-7803-6472-4

Type

conf

DOI

10.1109/DRC.2000.877072

Filename

877072