Title :
A 6fJ/step, 5.5ps time-to-digital converter for a digital PLL in 40nm digital LP CMOS
Author :
Borremans, J. ; Vengattarmane, K. ; Craninckx, J.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
A compact (0.01mm2) coarse-fine time-to-digital converter (TDC) in 40nm LP CMOS achieves 5.5ps resolution using parallel delay lines. A 6fJ/conversion step efficiency is achieved thanks to efficient residue calculation. A 0.8LSB single-shot precision and low DNL are reached thanks to simple calibration which is possible in fractional-N PLLs. Further, metastability avoidance and digital error correction are implemented. This 14-bit architecture operates at a 40MS/s reference clock.
Keywords :
CMOS integrated circuits; convertors; delay lines; phase locked loops; 6fJ/conversion step efficiency; LSB single-shot precision; calibration; compact coarse-fine time-to-digital converter; digital LP CMOS; digital PLL; digital error correction; fractional-N PLL; metastability avoidance; parallel delay line; residue calculation; size 40 nm; Calibration; Delay lines; Dynamic range; Error correction; Metastasis; Oscillators; Phase frequency detector; Phase locked loops; Signal resolution; Voltage;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-6240-7
DOI :
10.1109/RFIC.2010.5477312
